pRAM-256

pRAM-256 neurocomputer with on-chip learning

General Description

The pRAM-256 is a versatile neural network processor with an on-chip learning unit. It offers the flexibility of a software solution with the speed of hardware. Connections between the pRAM neurons are reconfigurable which allows a network's architecture to be modified at any time. The pRAM-256 can complete one pass of the training process, training all 256 pRAMs, in less than 0.25 ms when operating at the maximum clock speed of 33 MHz. Because of the high number of pRAMs supported by the pRAM-256, a typical neural network can be built using a single pRAM Module. Several pRAM Modules can operate in parallel so that larger networks can be built. The pRAM-256 is fabricated using an advanced sub-micron gate array semi-custom technology from GEC Plessey Semiconductors. The use of a 68 pin PGA package allows a compact neural network to be built into existing and future systems. Interfaces to EISA and VME bus systems have been defined and the current PC-based board is capable of carrying up to 5 pRAM-256 chips

Data Sheets

Data sheets are available in PDF.

• pRAM Data Sheet     (PDF)
• pRAM Timing Data    (PDF)
• pRAM Setup and Training Data   (PDF)

The data sheets are also available from the links below:

pRAM-256 data sheets

• architecture
• pin assignment
• pin descriptions
• internal registers
• memory mapping for weights and connections
• connection pointers
• functional description

pRAM-256 timing and bus signals

• timing
• data bus
• read/write cycle
• register access
• multiprocessor synchronisation
• reinforcement training signals
• chip reset

pRAM-256 configuration examples

The information below contains some examples of pRAM-256 implementations. These examples are not exhaustive, but are to give some hints on building systems using the pRAM-256.
We are currently using the Lattice in-system programmable (isp) FPGAs to interface the pRAM-256 to external hardware. This allows both the interface and the neural network to be reconfigured without rewiring the circuit.

• synaptic connections, making non-learning pRAMs
• pyramidal networks
• training pyramidal structures
• competitive learning
• local (Hebbian) learning
• handling real-valued inputs
• input and output of training and testing data

Applications of the pRAM

A PC interface card using the EISA bus has been designed for the pRAM-256 chip.
The board can be configured to support any possible pRAM network architecture by downloading a short connection-pointer file to an area of on-board RAM.
The spike output of the pRAM-256 can be converted to a mean firing frequency using the on-board FPGA which itself is in-system programmable. Different logic functions can be performed directly in hardware so long as they can be fitted into the FPGA.

Thus a single pRAM board can be used to investigate many different network topologies.

• (image) pRAM chip and PC board
• Automatic Target Recognition using pRAMs (pdf)
• ATM Connection Admission Control using pRAM networks (pdf)
• The Effects of Space Radiation on Artificial Neural Networks
• Building a Learning System using Probabilistic RAM Nets
• Standalone Hardware-based Learning System (pdf) Figures (pdf) Journal
• Review of Hardware pRAMs (pdf)
• A standalone hardware-based learning system (pdf)