The aim of this research was to characterise the performance of a VLSI neural network in the learning and execution of an image recognition task whilst exposed to the space radiation environment. The VLSI network was subjected to high-energy particles which were highly likely to create single-event upsets (SEUs) whereby the state of a given circuit element was changed. The level of irradiation to which the circuit was ultimately tested far exceeded that which would be experienced by a low earth orbit (LEO) satellite.
The pRAM-256 neural processor, designed at King's College London, was the subject of this study. The critical parts of the neural network architecture were identified for these harsh radiation environments. These are: the reward and penalty learning-rate registers in the pRAM-256 chip and the connectivity pointers in external RAM, especially those relating to the output layer of the network.
In order to place the pRAM electronics into the evacuated test chamber the PC bus was extended to approximately 0.75m in length. This was achieved using a 40-way ribbon cable and two PCB boards used as interfaces between the ISA bus and ribbon cable connectors. A separate power supply was used to power the board which was protected from drawing high currents by a latchup protection switch.
The neural network was applied to an image identification problem such as the detection of land-water boundaries obtained from IR earth imaging satellites. The importance of such on-board processing of images, without error, is that the processed data is in a compressed form and this makes fewer demands on the on-board power supply. The VLSI neural network successfully processed images, even in the presence of a large number of SEUs. Only when the radiation was many orders of magnitude above that expected, did noticeable degradation of the processed images occur. In most cases, an isolated SEU had no effect of the processing operation apart from a transient affecting a single bit of data.
The contribution of King's College was in the preparation and supply of a PC-based interface card which could carry from one to five pRAM-256 chips. A custom printed circuit board was constructed which could carry out the experiments planned. This form of interface board allowed the bus to be extended as stated above, so that only the board needed to be placed in the evacuated chamber. Three PCBs were produced as part of the development; Issue 3 being the latest version. A number of succesful experiments were carried out which have demonstrated the advantages of a neural processing device over a conventional processor in the presence of SEUs.
May 1999