Internal register addresses

Three internal registers are implemented inside the chip. Two of these registers, r and rl, are for the learning and decay rates of the on-chip learning unit. The third register, FBPL, selects the feedback polynomial of the pseudo random number generator. These registers are 16-bit write-only registers. They can be accessed by first halting the chip and, when HALT_ACK is TRUE, asserting the corresponding address onto the address bus. Data on the data bus will be transferred to the selected register on the rising edge of the RRW signal (r and rl) or when RRW is low, for the FBPL register. When A1:A2 = 11 RRW can be either state.

The feedback polynomial comprises five terms which are selected from the following tap points: {x6, x9, x15, x16, x21, x25}. This set of tap points has been selected to provide the highest number of irreducible polynomials from three feedback terms. The possible polynomials are listed in the following table. Since the x0 and x31 terms must be included in all irreducible polynomials, only three terms need be selected. The selection is achieved by writing the number shown to the FBPL register. Three bits are required for the selection of each term, therefore a 9-bit number is required to specify the feedback polynomial selected. A '1' will be injected into the shift register after a RESET for the purpose of auto-starting the random number generator.

Definition of the FBPL register

More data