Address definition and External memory management
The memory address space requires minimal address decoding. It is divided into 512 pages with a page size of 128 words (256 bytes) and the address bus is 16 bits wide. The pRAM number within the pRAM-256 defines the high byte of the address. The low byte is used to address the weights (au) or the connection pointers of that pRAM. Bit 7 of the low byte is used to select the page for au (when '1') or the page for connection pointers (when '0'). The memory map of the external memory and the definition of the RAM address are shown in the following figure. The first Connection Pointer (CP) to be fetched is at the lowest address and defines the most-significant bit of the weight address (au).
High speed static RAM is desirable for the external memory. The access time
of the SRAM should be less than 25ns when the chip is clocked at 33MHz.
Address definition and External memory management