Pin descriptions

NameTypeDescriptions
D0 to D15BI-DIRBi-directional data bus connected to external SRAM and controlled by WE. During normal operation, connection pointers and memory contents are transferred from the SRAM to the pRAM-256 using this bus. When HALT is active and a valid address is set, data may be transferred to the internal registers at the rising edge of RRW.
A1 to A15TRI
(A1, A2 -
BI-DIR)
Address bus to control the transfer of data to or from the pRAM-256 from the external SRAM. A3 to A15 are outputs which are tri-stated when HALT is active. A1 and A2 are normally outputs but when HALT is active, these become inputs which are used to address the internal registers .
WETRIThis is the write enable signal from the pRAM-256 to external SRAM It is tri-stated when HALT is active. Active LOW.
SOP1O/PStart Of pRAM 1: This signal is set HIGH by the pRAM-256 to indicate the start of the first pRAM process. It is set LOW at the end of the first pRAM process.
RTSOpen DrainReady To Start: This signal synchronises the inter-module communications and indicates that the processing of one of the 256 pRAMs has been completed. It should be connected to the CTS and the RTS pins of the other pRAM-256 modules (if present). An open drain gate is used to simplify the connection. If a single pRAM-256 is used, this output may be ignored. RTS goes LOW when each of the 256 pRAM processes starts and goes HIGH when the process is completed.
CTSI/PClear to Start: This signal tells the pRAM-256 that all other modules are ready to begin processing the next pRAM. It is active HIGH. If a single pRAM-256 is used, this pin should be tied HIGH or to RTS.
pRAM_OUTO/PThis is the output of the pRAM currently being processed. The data is valid as soon as RTS goes HIGH. It should be connected to a serial input (NORTH, SOUTH, EAST or WEST) of another module (if present), or this signal may be read by external circuitry. 256 bits of data are output between active transitions of SOP1.
NORTHI/PSerial input which accepts the pRAM outputs from another module. Data on the serial input is latched into on-chip memory at the trailing edge of CTS.
EAST
SOUTH
WEST
I/PAs NORTH. Unused inputs may be used for external inputs as EXT.
EXTI/PSerial input for external inputs. It can accept up to 256 bits of data in one SOP1 frame. Data is latched at the trailing edge of CTS.
HALTI/PUsed to halt the module at the end of the current pass. It is active LOW.
ACK_HALTO/PThis signal acknowledges the halt request. If training is disabled, ACK_HALT is set at the end of PASS 1. However, if training is enabled, ACK_HALT is set at the end of PASS 2. It is active HIGH. When halted, all control and data lines except A1 and A2 are tri-stated to allow an external device to access the SRAM or to write to the pRAM-256 internal registers.
TRAINI/PTraining is enabled when TRAIN is set to HIGH.
ACK_TRAINO/PThis signal acknowledges the enable training request. This is set at the end of PASS 1. It is active HIGH.
RESETI/PMaster reset. Active LOW.
CLKI/PClock signal, maximum 33MHz, CMOS levels.
REWARDI/PExternal environment inputs used during reinforcement training. These must be held in a constant state by external circuitry during PASS 2. Active HIGH.
RRWI/P This is the write enable control of the three internal registers, r, rl and FBPL. r and rl are the learning rate and decay rate used by the on-chip learning unit. FBPL controls the selection of the feedback polynomial of the pseudo random number generator. The module must be halted before data can be transferred into these registers at the rising edge of RRW. Note: a special procedure is required to control the address bus (A1-A2).

More data


T G Clarkson, August 1995