68 pin PGA package
| A2 | WE | B9 | PENALTY | F10 | n/c | K4 | A4 |
|---|---|---|---|---|---|---|---|
| A3 | RRW | B10 | TRAIN | F11 | n/c | K5 | A5 |
| A4 | RTS | B11 | ACK_TRAIN | G1 | D10 | K6 | A7 |
| A5 | CTS | C1 | D3 | G2 | D9 | K7 | A9 |
| A6 | NORTH | C2 | D2 | G10 | n/c | K8 | GND |
| A7 | SOUTH | C10 | n/c | G11 | n/c | K9 | A12 |
| A8 | Vdd | C11 | HALT | H1 | D11 | K10 | A15 |
| A9 | REWARD | D1 | Vdd | H2 | GND | K11 | ACK_HALT |
| A10 | CLK | D2 | D4 | H10 | n/c | L2 | A1 |
| B1 | D1 | D10 | GND | H11 | Vdd | L3 | A3 |
| B2 | D0 | D11 | RESET | J1 | D13 | L4 | Vdd |
| B3 | SOP1 | E1 | D6 | J2 | D12 | L5 | A6 |
| B4 | GND | E2 | D5 | J10 | n/c | L6 | A8 |
| B5 | PRAM_OUT | E10 | n/c | J11 | n/c | L7 | A10 |
| B6 | EAST | E11 | n/c | K1 | D14 | L8 | A11 |
| B7 | WEST | F1 | D8 | K2 | D15 | L9 | A13 |
| B8 | EXT | F2 | D7 | K3 | A2 | L10 | A14 |
The CMOS process used to fabricate the pRAM-256 is fully static. Therefore the device may be halted and operated in a standby mode with no loss of data. The pRAM-256 may also be operated at supply voltages below 5V (e.g. 3V) with a much lower power consumption but with a reduced operating speed.