Each pRAM-256 has 256 pRAMs which are processed serially at high speed.
The operation of a pRAM Module is performed in two passes, PASS1 and PASS2.
PASS1: is a process which calculates the new outputs for the 256 pRAMs.
This requires 256 non-learning pRAM cycles.
PASS2: is an optional process which updates the weights of the 256 pRAMs.
These weights are stored in external SRAM. This pass uses 256 learning
pRAM cycles. PASS2 may be omitted if training is not required, in which
case TRAIN is LOW. Faster pRAM processing is possible when training is
disabled.
Non-learning pRAM cycle: This process calculates the new pRAM outputs. In a non-learning cycle, the pRAM-256 fetches the six Connection Pointers from the SRAM and decodes them to generate an Input Vector. The Input Vector then forms part of the address used by the pRAM-256 to fetch the selected weight from the SRAM. Finally, the pRAM-256 executes the pRAM algorithm by comparing the weight to a random number and storing the result (1 or 0) in the internal Output List. The result is broadcast at the same time to the other modules from pRAM_OUT. The Input Vector formed in this cycle is saved in an on-chip cache memory for PASS2 (if executed).
Learning pRAM cycle: This process updates a pRAM weight. In a learning cycle, the pRAM-256 fetches the Connection Pointers for r and p from the SRAM and decodes them to generate the reward and penalty environment signals for the on-chip learning unit. By using the Input Vector, which is generated in the corresponding non-learning pRAM cycle above, a is fetched from the SRAM and updated according to the learning rule. The updated a is then saved in the external SRAM.
Connection Pointer: A 12 bit binary number which specifies the source of data for pRAM inputs and the pRAM reward and penalty inputs. The Connection Pointer table is held in the external SRAM; this table must be defined before pRAM processing starts and may be redefined at any time by asserting the HALT input and waiting for HALT_ACK.