Names are assigned to the pins so that the PALASM equations can be built. These names have no significance outside PALASM.
Note the use of a simulation segment to test the design. This is later used to test the GAL in the programmer to verify that it has been programmed correctly.
;PALASM Design Description ;---------------------------------- Declaration Segment ------------ TITLE pRAM PC_interface Address Decoder PATTERN pRAM97A.pds REVISION H AUTHOR Trevor Clarkson COMPANY EEE KCL DATE 30/05/97 CHIP decode PALCE20V8 ;---------------------------------- PIN Declarations --------------- PIN 1 AEN COMBINATORIAL ; INPUT PIN 2 A9 COMBINATORIAL ; INPUT PIN 3 A8 COMBINATORIAL ; INPUT PIN 4 A7 COMBINATORIAL ; INPUT PIN 5 A6 COMBINATORIAL ; INPUT PIN 6 A5 COMBINATORIAL ; INPUT PIN 7 A4 COMBINATORIAL ; INPUT PIN 8 A3 COMBINATORIAL ; INPUT PIN 9 A2 COMBINATORIAL ; INPUT PIN 10 A1 COMBINATORIAL ; INPUT PIN 11 IOW COMBINATORIAL ; INPUT PIN 12 GND PIN 13 IOR COMBINATORIAL ; INPUT PIN 14 ACK_HALT COMBINATORIAL ; INPUT PIN 15 PLS_EN COMBINATORIAL ; OUTPUT PIN 16 BRDW COMBINATORIAL ; OUTPUT PIN 17 MOD_CTRL COMBINATORIAL ; OUTPUT PIN 18 RAM_ACCESS COMBINATORIAL ; OUTPUT PIN 19 IO_16 COMBINATORIAL ; OUTPUT PIN 20 LATCH_MOD COMBINATORIAL ; OUTPUT PIN 21 LATCH_ADD COMBINATORIAL ; OUTPUT PIN 22 P300 COMBINATORIAL ; OUTPUT PIN 23 P300IN COMBINATORIAL ; INPUT PIN 24 VCC ;PC address decoding functions (not all in this PAL) ;uses latched address to provide low-order address lines to pRAM/RAM ; A3 A2 A1 R/W Addr Function ; 0 0 0 R 300 MFF_0 ; W not used ; 0 0 1 R 302 MFF_1 ; W not used ; 0 1 0 R 304 MFF_2 ; W not used ; 0 1 1 R 306 MFF_3 ; W Latch Module Number ; 1 0 0 R 308 PLS_Status (pRAM status) ; W PLS_Control (pRAM control) ; 1 0 1 R 30A Weight/Connection- ; W Pointer RAM access ; 1 1 0 R 30C not used ; W Latched RAM address ; 1 1 1 R 30E not used ; W pRAM_256 module control ; ; NB. IO_16 must be tri-stated when not in use ;----------------------------------- Boolean Equation Segment ------ EQUATIONS /P300 = A9*A8*/A7*/A6*/A5*/A4*/IOR + A9*A8*/A7*/A6*/A5*/A4*/IOW /BRDW = /P300IN * /IOW /PLS_EN = /P300IN*/A3*/IOR + /P300IN*A3*/A2*/A1 ; MOD_CTRL is active HIGH MOD_CTRL = ACK_HALT * /BRDW * A3 * A2 * A1 * /IOW ; RAM_ACCESS is active HIGH RAM_ACCESS = ACK_HALT * /P300IN * A3 * /A2 * A1 IO_16 = GND IO_16.TRST = /P300IN ; enable 16-bit transfers ; LATCH_MOD is active HIGH LATCH_MOD = /BRDW * /A3 * A2 * A1 ; LATCH_ADD is active HIGH LATCH_ADD = /BRDW * A3 * A2 * /A1 ;----------------------------------- Simulation Segment ------------ SIMULATION TRACE_ON A9 A8 A7 A6 A5 A4 IOR /IOW /BRDW /PLS_EN MOD_CTRL RAM_ACCESS IO_16 LATCH_MOD LATCH_ADD ACK_HALT /P300 /P300IN SETF /A9 /A8 /A7 /A6 /A5 /A4 /A3 /A2 /A1 IOR IOW /ACK_HALT /P300IN SETF /IOW ; test P300 doesn't respond SETF IOW /IOR ; test P300 doesn't respond SETF IOR SETF A9 A8 /A7 /A6 /A5 /A4 /IOR /P300IN SETF A1 SETF A2 /A1 SETF A1 ; read mff0-3 SETF IOR /IOW ; test P300 and BRDW SETF /A3 A2 A1 ; test Latch Module No SETF IOW A3 A2 A1 ; MOD-CTRL not active until ACK_HALT SETF ACK_HALT /IOW SETF IOW /ACK_HALT SETF A3 /A2 A1 ; check RAM_ACCESS SETF ACK_HALT /IOW SETF /ACK_HALT IOW SETF ACK_HALT /IOR ; check READ and WRITE to RAM SETF IOR P300IN SETF /A3 A2 A1 SETF /ACK_HALT /P300IN SETF IOW SETF /A3 A2 A1 /IOW ; check LATCH_MOD SETF IOW SETF A3 A2 /A1 SETF /IOW ; check LATCH_ADD SETF /A3 /A2 /A1 ; shouldn't happen normally TRACE_OFF ;-------------------------------------------------------------------
PALASM4 PAL ASSEMBLER - MARKET RELEASE (10-5-90)
(C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1990
TITLE :pRAM PC_interface Address DecoderAUTHOR :Trevor Clarkson
PATTERN :pRAM97A.pds COMPANY:EEE KCL
REVISION:H DATE :30/05/97
PAL20V8
DECODE
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
0 ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
1 X--- X--- -X-- -X-- -X-- -X-- ---- ---- ---- ---X
2 X--- X--- -X-- -X-- -X-- -X-- ---- ---- ---- -X--
3 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
4 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
5 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
6 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
7 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
8 ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
9 ---- ---- ---- ---- ---- ---- X--- X--X -X-- ----
10 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
11 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
12 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
13 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
14 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
15 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
16 ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
17 ---- ---- ---- ---- ---- ---- -X-- X--X X--- ----
18 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
19 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
20 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
21 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
22 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
23 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
24 ---- ---X ---- ---- ---- ---- ---- ---- ---- ----
25 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
26 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
27 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
28 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
29 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
30 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
31 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
32 ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
33 ---- ---X ---- ---- ---- ---- X--- -X-- X-X- ----
34 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
35 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
36 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
37 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
38 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
39 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
40 ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
41 ---- ---- ---- ---- ---- ---- X--- X--X X-X- -X--
42 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
43 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
44 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
45 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
46 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
47 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
48 ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
49 ---- ---X ---- ---- ---- ---- ---- ---- ---- -X--
50 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
51 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
52 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
53 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
54 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
55 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
56 ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
57 ---- ---X ---- ---- ---- ---- -X-- ---- ---- ---X
58 ---- ---X ---- ---- ---- ---- X--- -X-- -X-- ----
59 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
60 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
61 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
62 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
63 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
SUMMARY
-------
OUTPUT PINS: 11111222
56789012
POLARITY FUSES: XX-----X
OUTPUT PINS: 11111222
56789012
SL0 FUSES: --------
OUTPUT PINS: 11111222
56789012
PTERM DIS. FUSES: --------
PTERM DIS. FUSES: --------
PTERM DIS. FUSES: --------
PTERM DIS. FUSES: --------
PTERM DIS. FUSES: --------
PTERM DIS. FUSES: --------
PTERM DIS. FUSES: --------
PTERM DIS. FUSES: --------
SG0 FUSE: -
SG1 FUSE: -
SIGNATURE FUSES: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
TOTAL FUSES BLOWN = 716
Compare this segment with the HL format below.
PALASM4 PLDSIM - MARKET RELEASE (9-25-90)
(C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1990
PALASM SIMULATION HISTORY LISTING
Title : pRAM PC_interface Addres Author : Trevor Clarkson
Pattern : pRAM97A.pds Company : EEE KCL
Revision : H Date : 30/05/97
PAL20V8
Page : 1
gggggggggggggggggggggggggg
AEN XXXXXXXXXXXXXXXXXXXXXXXXXX
A9 LLLLHHHHHHHHHHHHHHHHHHHHHH
A8 LLLLHHHHHHHHHHHHHHHHHHHHHH
A7 LLLLLLLLLLLLLLLLLLLLLLLLLL
A6 LLLLLLLLLLLLLLLLLLLLLLLLLL
A5 LLLLLLLLLLLLLLLLLLLLLLLLLL
A4 LLLLLLLLLLLLLLLLLLLLLLLLLL
A3 LLLLLLLLLLHHHHHHHHLLLLLHHL
A2 LLLLLLHHHHHHHLLLLLHHHHHHHL
A1 LLLLLHLHHHHHHHHHHHHHHHHLLL
IOW HLHHHHHHLLHLHHLHHHHHHLHHLL
GND LLLLLLLLLLLLLLLLLLLLLLLLLL
IOR HHLHLLLLHHHHHHHHLHHHHHHHHH
ACK_HALT LLLLLLLLLLLHLLHLHHHLLLLLLL
PLS_EN HHHHLLLLHHHHHHHHHHHHHHHHHH
BRDW HHHHHHHHLLHLHHLHHHHHHLHHLL
MOD_CTRL LLLLLLLLLLLHLLLLLLLLLLLLLL
RAM_ACCESS LLLLLLLLLLLLLLHLHLLLLLLLLL
IO_16 ZZZZLLLLLLZLZZLZLZZZZLZZLL
LATCH_MOD LLLLLLLLHHLLLLLLLLLLLHLLLL
LATCH_ADD LLLLLLLLLLLLLLLLLLLLLLLLHL
P300 HHHHLLLLLLHLHHLHLHHHHLHHLL
P300IN HHHHLLLLLLHLHHLHLHHHHLHHLL
VCC HHHHHHHHHHHHHHHHHHHHHHHHHH
In this version, the test vectors follow after the fuse-map section. The programmer applies electrical signals to the programmed GAL to verify that it works to this specification.
PALASM4 PAL ASSEMBLER - MARKET RELEASE (10-5-90) (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1990 TITLE :pRAM PC_interface Address DecoderAUTHOR :Trevor Clarkson PATTERN :pRAM97A.pds COMPANY:EEE KCL REVISION:H DATE :30/05/97 PAL20V8 DECODE* QV0026* QP24* QF2706* G0*F0* L0000 1111111111111111111111111111111111111111* L0040 0111011110111011101110111111111111111110* L0080 0111011110111011101110111111111111111011* L0120 0000000000000000000000000000000000000000* L0160 0000000000000000000000000000000000000000* L0200 0000000000000000000000000000000000000000* L0240 0000000000000000000000000000000000000000* L0280 0000000000000000000000000000000000000000* L0320 1111111111111111111111111111111111111111* L0360 1111111111111111111111110111011010111111* L0400 0000000000000000000000000000000000000000* L0440 0000000000000000000000000000000000000000* L0480 0000000000000000000000000000000000000000* L0520 0000000000000000000000000000000000000000* L0560 0000000000000000000000000000000000000000* L0600 0000000000000000000000000000000000000000* L0640 1111111111111111111111111111111111111111* L0680 1111111111111111111111111011011001111111* L0720 0000000000000000000000000000000000000000* L0760 0000000000000000000000000000000000000000* L0800 0000000000000000000000000000000000000000* L0840 0000000000000000000000000000000000000000* L0880 0000000000000000000000000000000000000000* L0920 0000000000000000000000000000000000000000* L0960 1111111011111111111111111111111111111111* L1000 0000000000000000000000000000000000000000* L1040 0000000000000000000000000000000000000000* L1080 0000000000000000000000000000000000000000* L1120 0000000000000000000000000000000000000000* L1160 0000000000000000000000000000000000000000* L1200 0000000000000000000000000000000000000000* L1240 0000000000000000000000000000000000000000* L1280 1111111111111111111111111111111111111111* L1320 1111111011111111111111110111101101011111* L1360 0000000000000000000000000000000000000000* L1400 0000000000000000000000000000000000000000* L1440 0000000000000000000000000000000000000000* L1480 0000000000000000000000000000000000000000* L1520 0000000000000000000000000000000000000000* L1560 0000000000000000000000000000000000000000* L1600 1111111111111111111111111111111111111111* L1640 1111111111111111111111110111011001011011* L1680 0000000000000000000000000000000000000000* L1720 0000000000000000000000000000000000000000* L1760 0000000000000000000000000000000000000000* L1800 0000000000000000000000000000000000000000* L1840 0000000000000000000000000000000000000000* L1880 0000000000000000000000000000000000000000* L1920 1111111111111111111111111111111111111111* L1960 1111111011111111111111111111111111111011* L2000 0000000000000000000000000000000000000000* L2040 0000000000000000000000000000000000000000* L2080 0000000000000000000000000000000000000000* L2120 0000000000000000000000000000000000000000* L2160 0000000000000000000000000000000000000000* L2200 0000000000000000000000000000000000000000* L2240 1111111111111111111111111111111111111111* L2280 1111111011111111111111111011111111111110* L2320 1111111011111111111111110111101110111111* L2360 0000000000000000000000000000000000000000* L2400 0000000000000000000000000000000000000000* L2440 0000000000000000000000000000000000000000* L2480 0000000000000000000000000000000000000000* L2520 0000000000000000000000000000000000000000* L2560 0111110000000000000000000000000000000000* L2600 0000000000000000000000000000000011111111* L2640 1111111111111111111111111111111111111111* L2680 11111111111111111111111111* V0001 X0000000001N10HHLLZLLH1N* V0002 X0000000000N10HHLLZLLH1N* V0003 X0000000001N00HHLLZLLH1N* V0004 X0000000001N10HHLLZLLH1N* V0005 X1100000001N00LHLLLLLL0N* V0006 X1100000011N00LHLLLLLL0N* V0007 X1100000101N00LHLLLLLL0N* V0008 X1100000111N00LHLLLLLL0N* V0009 X1100000110N10HLLLLHLL0N* V0010 X1100000110N10HLLLLHLL0N* V0011 X1100001111N10HHLLZLLH1N* V0012 X1100001110N11HLHLLLLL0N* V0013 X1100001111N10HHLLZLLH1N* V0014 X1100001011N10HHLLZLLH1N* V0015 X1100001010N11HLLHLLLL0N* V0016 X1100001011N10HHLLZLLH1N* V0017 X1100001011N01HHLHLLLL0N* V0018 X1100001011N11HHLLZLLH1N* V0019 X1100000111N11HHLLZLLH1N* V0020 X1100000111N10HHLLZLLH1N* V0021 X1100000111N10HHLLZLLH1N* V0022 X1100000110N10HLLLLHLL0N* V0023 X1100000111N10HHLLZLLH1N* V0024 X1100001101N10HHLLZLLH1N* V0025 X1100001100N10HLLLLLHL0N* V0026 X1100000000N10HLLLLLLL0N* C5752*
TITLE: pRAM PC_interface Address Decoder
PATTERN: pRAM97A.pds
REVISION: H
AUTHOR: Trevor Clarkson
COMPANY: EEE KCL
DATE: 30/05/97
MACRO: DECODE
PAL20V8
+----++----+
COM AEN +-¦ 1 ++ 24 ¦-+ VCC
COM A9 +-¦ 2 23 ¦-+ P300IN COM
COM A8 +-¦ 3 22 ¦-+ P300 COM
COM A7 +-¦ 4 21 ¦-+ LATCH_ADCOM
COM A6 +-¦ 5 20 ¦-+ LATCH_MOCOM
COM A5 +-¦ 6 19 ¦-+ IO_16 COM
COM A4 +-¦ 7 18 ¦-+ RAM_ACCECOM
COM A3 +-¦ 8 17 ¦-+ MOD_CTRLCOM
COM A2 +-¦ 9 16 ¦-+ BRDW COM
COM A1 +-¦ 10 15 ¦-+ PLS_EN COM
COM IOW +-¦ 11 14 ¦-+ ACK_HALTCOM
COM IOW +-¦ 11 14 ¦-+ ACK_HALTCOM
GND +-¦ 12 13 ¦-+ IOR COM
+----------+