2. Programmable Logic (e.g. PALs)
3. Semi-Custom (Gate Arrays and Standard Cells)
4. Full-Custom (Handcrafted Devices)
The development time and the cost increases as we move from Standard Devices to Full-Custom Design (see chart below)
`X` is used to represent an intact fuse. The three symbols below for a two-imput AND gate are equivalent.
PALs come in different configurations in order to suit different types of applications. An AND-OR cell implementation which is the basic PAL cell, is given below:
Other possible configurations are:
1. Programmable Input/Output (includes an added capability of a programmable enable line)
2. Registered Output with Feedback (stores the product term in a flip-flop)
3. Arithemtic PAL Cell (incorporates an EX-OR and gated feedback and is used for basic arithmetic operations)
(For examples of the above see Figures 2.54, 2.55 and 2.56 in [Almaini, 1994], see Reading List)
* Ease of design
* Performance
* Reliability
* Cost Savings
COMBINATIONAL:
* Number of inputs
* Number of outputs
* Number of product terms per output
* Speed
* Power consumption
* Reprogrammable ?
REGISTERED:
* + Number of Registers
The steps for PAL design and implementation are given below:
Programmable logic development systems are available to simplify the design, programming and testing of PAL and similar programmable logic devices. These systems consist of a programmer plus suitable adaptors. One such system employs a PAL assembler and simulator (PALASM) design adaptor and a programming testing (P/T) adaptor. The data are entered to the PALASM via a terminal in the form of Boolean equations. The PALASM design adaptor translates the equations into a fuse pattern which is stored in a RAM. The P/T adaptor is then used to program the device by blowing the appropriate fuses according to the fuse pattern.
PAL design steps using PALASM are given below:
1. Choose device
2. Build equations:
B = /A ; inverter
E = C * D ; AND
H = F + G ; OR
Note:
W = /X + /Y ; NAND or /(X * Y)
W = /X + /Y ; NOR or /(X + Y)
3. Label pins
4. Build simulation
- for logic test
- for product test after programming
5. Assemble
- fuse map
- JEDEC file - programmer
6. Programming
PAL programmer (like EPROM programmer)
A design example using PALASM can be found in pp.125-126 of [Almaini,1994] (see reading list). A more advanced example can be found in pp. 211-214.
Other examples of PALASM source and output files are given here.
A PLA has a second programmable field as shown below compared to a PAL:
The same programming tools are available as for PALs.
GATE ARRAYS
or characterised predesigned cells:
STANDARD CELLS
The design cycle for Semi-Custom design is given below:
* GAs are available in ECL, CMOS and bipolar technologies
* GAs are available in a variety of gate counts from a few hundred up to 40000
* Designer needs to know nothing about the transistor and circuit level
Comparison with Full Custom Design:
* LOW development cost
* SHORT production time
* Silicon area not efficiently utilised (some redundant gates)
Therefore GAs are not very attractive for high volume applications in which silicon cost becomes a major factor in the overall production costs. GAs are practical however in low- to medium- volume applications or in applications that require quick turn-around.
* Designer takes these blocks and connects them together to make a circuit with the required function
* Small redundant area
* Higher packing density than in GAs
* More expensive than GAs because each design will use a different configuration of standard cells requiring thus a full mask set
** Combine the advantages of Programmable Logic Devices (PLDs) and Gate Arrays
i.e., from GAs:
* short development cycle
* low cost compared to full-custom
and from PLDs:
* safer, because they are well tested
* shorter development cycle than GAs
* easy prototyping and low risk
** FPGAs overcome the drawbacks of PLDs
i.e.,
* rigid architecture
* low gate count and gate utilisation
* the requirement of glue logic
FPGAs have a number of GAL-like internal blocks. For example, Lattice call these Generic Logic Blocks.
A Generic Logic Block (GLB) (see below)
can exist within a Lattice FPGA (see below):
Full custom design allows complete control over the placement, size and interconnetctions of all transistors. The design is made down to transistor level.
Advantages
* Minimum silicon area and thus cost reduction.
* Freedom of placement of transistors to make the required logic blocks, provided the design rules of fabrication are obeyed.
* Maximum performance obtained.
Disadvantages
* Needs full mask set which is expensive.
* Slow design.
* Needs skilled and experienced designers.
A full-custom design overview is shown below:
The full custom design is an iterative procedure, as it can be seen from the above diagram, which an extremely simplified one. In practice there are a lot of loops but only some of them are indicated on the diagram. An important point is that testing should be done by simulation before building the chip in silicon.
The System Specification constitutes the requirements of the system to be designed.
The Logic Design results from the specification: is the making of the internal logic design including the internal design of the particular modules of the system.
Network encoding is the extraction of a schematic or physical layout in such a way so that simulation can be done to it. This is followed by the Logic Simulation (i.e. modelling of the system and verification of the design) and then back to the logic design if the system does not work. This is the first major iteration. An iteration may exist also between the first two blocks, i.e., after an initial system specification is made, the designer starts thinking about the system design which might make him/her to think of ways of changing the system specification.
The Network Encoding usually has some way of checking feasibility. This is done by software. This testing might well affect the system specification so one might go back and change it. Thus, there will be a lot of iteration going on until the designer is happy with the logic simulation of the system.
In writing the initial system specification, the designer probably knows what sort of waveforms the inputs and outputs expect. Therefore some Waveform Design can be done and must be done in parallel with the Logic Simulation. The waveforms should also be encoded in order to fit into the simulators.
During the Logic Design one has to think about testing as well, i.e., think about building a self-test facility inside the system.
The Layout Design stage comes along when the designer is satisfied with the logic design. This can be automatic (using auto layout facilities like Silicon Compilers - see below) or manual . In doing manual Layout Design, the designer checks the geometries and the validity of the system. Having finished the layout which passed the geometrical Design Rules then Circuit Simulation is performed. The Design Rules are well documented specifications listing minimum widths of features, minimum spacings allowable between adjacent features, overlap requirements, and other measurements that are compatible with a given process. At the Circuit Simulation stage, a netlist is obtained again by extracting the circuit encoding from the layout and do logic simulation so as to confirm that the circuit serves its purpose. It has to be pointed out, that when extraction from the layout is made, not only the transistors are extracted, but also parasitic elements (usually in extraction of resistances). This extraction of a more realistic circuit from the layout is what makes the circuit simulation extremely important.
When the design is completed, it is put though a mask which is actually a Pattern Generation process, to produce a sort of intermediate format for mass manufasturing. This is put on a tape.
Certainly, testing is done as well (Test Pattern Generation) which is sent to the manufacturer.
Characteristics
* No need for skilled and experienced VLSI designer.
* Convert ground plan into a number of functional blocks.
* Use logic blocks such as ALUs, MPXs etc., and also parameterised logic blocks (e.g., RAM, ROM, PLA)
Most compilers are by:
(i) GENESIL (used for Microprocessor design)
(ii) ES2 (European Company)
(iii) CADENCE
The Solo series of software is a Silicon Compiler which comes with an extensive library which can be enlarged. The input is either by Schematic or Model (HDL)
Formal description of IC structures at the top level of the design process.
(i) ELLA (Electronic Logic Language)
Originates from the British military.
(ii) VHDL (Very High Speed Integrated Circuit HDL)
Has its origins at the USA Department of Defence. Has been used in aeroplanes both military and commercial.
So HDLs are used in applications where there is a need of a very high level of confidence that the design is correct.