Tutorial: 3 March 1998


Outline Answers

What these features are can be found from the notes/textbooks. E.g. pipelining also requires internal buffers in the processor to store the pipelined instructions.

How they increase the throughput is answered by:
Harvard architecture doubles the buses, so increases bus bandwidth. It also makes for more efficient use of the data and program buses.
Pipelining aims to ensure that no unused memory bus cycles exist - as this is the major bottleneck in a microprocessor system.
Delayed branching aims to minimise the number of prefetched instructions that need to be discarded when a BRANCH is executed.


PAL design steps are given below:

1. Choose device

2. Build equations:

3. Label pins

4. Build simulation

- for logic test

- for product test after programming

5. Assemble

- fuse map

- JEDEC file - programmer

6. Programming

PAL programmer (like EPROM programmer)

The design of FPGAs differ from the above:

because of the need to place and route the various logic blocks and signals.

The design cycle for Semi-Custom design is given below:

In addition to the PLACE and ROUTE steps of the FPGA, which occur in or after the COMPILE section, much more effort is required in the design verification and simulation.


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