4. A paged memory management system has a 32-bit virtual address. The page size is 2 kbytes and the maximum memory size is 16 Mbytes.(a) determine the number of entries in the address translation table,
(b) draw a diagram showing all the connections between the CPU, PMMU and memory,
(c) describe, step by step, how a memory access is made by the CPU for the two conditions, when a page mapping exists and when it does not exist.
(a) The number of entries is 16 M / 2 k = 8192 entries.
(b)
(c) If a page exists in memory, then when the PMMU receives the virtual page number, this is directly translated into a physical page number in the PMMU and the bus cycle proceeds without delay.
If a page does not exist in memory, the PMMU signals a Bus Error when it receives the virtual page number. This causes the O.S. to intervene to determine the cause of the error. For a Page Error, the O.S. needs to swap out a page from memory to make space for the new page. The page to swap out will be determined by the Least Recently Used algorithm or similar. The swapped out page is copied into backing storage (e.g. hard disk). Then the new page is copied into memory from the backing storage and the PMMU table is updated with the new virtual to physical page mapping. The original bus cycle can then continued from the point at which the Bus Error occurred.
(d) Give four similarities between the operation of a PMMU and a memory cache controller.The PMMU and cache controller share the following features: a swapping algorithm, a table of entries, a table of access rights and a backing storage.
5. Describe the features of RISC processor designs which provide(a) lower-cost integrated circuits,
(b) improved efficiency in the use of the data bus, and
(c) the potential for a higher rate of data processing,
compared to CISC designs.
5a. Compare and contrast the design route for a semi-custom gate-array with a field programmable gate array. Give examples of typical applications for each type of semiconductor device.
The semi-custom design includes more preliminary design stages as the internal structure is not fixed, as it is in the case of a FPGA.
For the same reasons, a testability analysis is required, which is not the case with a FPGA.
The simulation and test phases are quite similar for a semi-custom design or a FPGA, although the FPGA may be expected to be less complex.
The semi-custom design has applications in complex circuits and systems, such as DSP circuits, graphics controllers and micro-controllers.
The FPGA is employed in simpler circuits such as DRAM controllers, address decoders and simple sequencers.
6. Explain how the VME bus is arranged so that data may be transferred from one processor card to another using the backplane.The VME bus transfers data between two processor systems by the use of a common backplane and control signals. Arbitration circuits are also required a) local to each system and b) for the common bus. The basic VME bus has a 16-bit address and 24-bit data bus. The extended VME bus increases both these to 32 bits.(a) explain the levels of priority which are available to processor cards and explain why this is important,
(b) describe the arbitration process for the use of the VME bus through the use of handshake and control lines.
To transfer data from one system to another, a) an off-board address is generated, b) the local system arbitrates for the use of the bus, c) when the use of the bus is granted, resources in the remote system are addressed and d) if the remote system allows reading of the address, the data is returned with a DTACK handshake, else no data is returned and a bus error is flagged.
(a) owing to the daisy-chain process of Bus Grants (Figure), the left-most slot has the highest priority in gaining use of the bus. Therefore, the order in which the cards are placed in the rack affects the priority of service. This is important because the Bus Controller (Arbiter) must be placed in the left-most slot.
(b) The arbitration process on the VME bus uses a set of bus request, control and grant lines as shown in the figure.
6a. Describe the exception vector provision of the 68000 processor and show how this can be used to emulate a future hardware co-processor.The 68000 has a vector table starting at address 000000 in memory. This contains the usual RESET vector, a range of IRQ vectors and traps for Bus and Address Errors.
In addition, there is an Illegal Instruction trap and a Line 1010 and Line 1111 Emulator. The illegal instruction trap is called when an instruction is fetched which is not a valid 68000 instruction. The Line 1010/1111 Emulators are similar, except that these allow a subset of unused instruction codes to be handled differently. In this way, a programmer can invent "new" instructions which cause the processor to jump to these vectors for execution. In this way, a software routine would be called in response to the "new" instruction. A later version of the 68000 could use this code as a valid co-processor instruction so that the same process can now be executed by a hardware co-processor.