5. Describe a scheme whereby a memory management unit is able to control the microprocessor's access to certain areas of memory. The scheme should be able to separate Supervisor and User modes and Read-only and Read-Write areas of memory.A Paged Memory Management Unit (PMMU) is connected to a MC68010 microprocessor. The PMMU has 128 entries in its address translation table and 4M bytes of RAM are to be managed. Draw a diagram showing how the 68010 is connected to the RAM via the PMMU. Assuming that all the RAM is to be used, what is the page size in kilobytes?
How does the Operating System control the PMMU and how may it write directly to RAM without address translation?
5a. A memory management system in the form of the figure below allocates separate areas of memory for Program (Read-only) and Data (Read-Write) accesses.
Function codes from the microprocessor indicate the kind of memory cycle currently being executed; User program, User data, Supervisor program or Supervisor data. These codes are compared with the access rights register when a memory address is output within the range, Base to Base+Limit, for either the Program or Data areas.
If an inappropriate access is performed, e.g. an instruction fetch from the Data area, or a write to the Program area, then a bus error is signalled and the cycle may be aborted (using the 68000 BERR input for example).
5b.
Where Ak = 23, Ar = 21, Ap = 14, RAM = 4Mbytes.
The page size is 4MB/128 = 32 Kbytes.
5c. The O.S. writes to the PMMU internal registers to determine the current mapping of memory pages. This mapping will change when a page fault occurs or when a context change to another user (in a multi-user system) occurs.
A virtual memory system requires a backing storage (or swap space, usually on a hard disc) in order to swap in and out the various processes or parts of processes. The PMMU performs address translation using the table shown. Access protection uses the flags shown, allowing only the addresses generated by active processes to be translated or allowing pages to be fixed in memory.
If an address cannot be translated (no virtual to physical mapping currently exists) then a page fault is generated - probably flagged to the processor by a BERR input. This generates a TRAP to the operating system and a page is swapped into memory which contains the address requested. Pages are swapped out using the LRU algorithm, or similar. The bus cycle can then be completed from the point at which the page fault occurred.
6. Why is bus-bandwidth an important parameter in a modern microprocessor system?Without increasing the bus width, how may the effective bus-bandwidth be maximised? Give 3 examples.
Describe how the VME bus is used to transfer data between two processor systems.
Describe the arbitration process which must take place before the VME bus can be used by a system.
6a. Bus-bandwidth an important parameter because memory transfers are slower than transfers internal to the microprocessor. Therefore as much data as possible should be transferred in a single bus cycle.
6b. Without increasing the bus width, the effective bus-bandwidth may be maximised by:
a) using DRAM page-mode cycles where up to twice as many access cycles may be completed in a given time,
b) use of instruction pipelines, so that the bus is never idle,
c) use of a RISC architecture which eliminates multiple-word instructions, since instruction fetch cycles perform no data processing.
6c. The VME bus transfers data between two processor systems by the use of a common backplane and control signals. Arbitration circuits are also required a) local to each system and b) for the common bus.
The basic VME bus has a 16-bit address and 24-bit data bus. The extended VME bus increases both these to 32 bits.
To transfer data from one system to another, a) an off-board address is generated, b) the local system arbitrates for the use of the bus, c) when the use of the bus is granted, resources in the the remote system are addressed and d) if the remote system allows reading of the address, the data is returned with a DTACK handshake, else no data is returned and a bus error is flagged.
6d. The arbitration process on the VME bus uses a set of bus request, control and grant lines as shown in the figure.
1) a board requesting the use of the VME bus asserts /BR0. Assume this is system A3.
2) The VME arbiter (in left-most slot) asserts /BG0out when the bus is free. This bus-grant is first offered to A2 as a daisy-chained signal. If A2 did not generate the bus request, then it must pass the /BG0 signal on to the next system - /BG0in on A2 is passed to /BG0out.
3) A3 receives /BG0in and immediately asserts /BBSY (bus busy). /BBSY is held low until the transfer is complete. Either a single word is transferred (arbitrate each cycle) or a block transfer takes place (arbitrate once at the start).
4) /BCLR can be asserted by the arbiter to force all systems to terminate their use of the bus. This can be used to terminate a long block transfer so that the bus can be used by other systems.