A scheme is required which restricts memory access types to certain areas in memory.
Most 8-bit microprocessors do not distinguish between memory access types. 16/32 bit microprocessors do - for example, the MC68000 has three function code pins (FC0-2) which give the following information.
| FC2-0 | Cycle Type |
|---|---|
|
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 |
(not used) USER data USER program (not used) (not used) SUPERVISOR data SUPERVISOR program Int Ack Cycle |
BERR will cause a TRAP (interrupt) and the Operating System (O.S.) is called on to report and fix, if possible, the error.
In order to give each process a unique address space, address translation is used to position programs and data in memory, transparently to the programmer and to the processor.
The address translation is under the control of the O.S. and requires both software and hardware for implementation.
Separate areas for program and data are required, since the program must be write-protected. The access rights determine which user can read/write each segment.
One solution is to arrange that only part of a task resides in memory at any time, with the remainder of the program or data areas being held on some backing storage. As required, parts of a task are swapped out and swapped into main memory for execution, since the processor can only fetch one instruction at a time, and can only write to one address location at a time.
The address space from the processor is similarly divided into pages of the same size. These are called the LOGICAL or VIRTUAL pages.
The pages in RAM are called the PHYSICAL pages.
A PMMU maintains a mapping between LOGICAL and PHYSICAL pages as shown, with a set of access permissions.
When an address is specified by the CPU, for example an address in logical page 17, then this is translated by the PMMU into a physical address - in page 2, using the example shown.
The PMMU uses Content Addressable Memory (CAM) for the logical page registers. CAM is a special form of memory, which does not have an address decoder as does conventional memory. In CAM, all memory locations monitor the incoming DATA and only the memory location whose contents match the incoming DATA responds.
In the diagram, an incoming logical page 5, causes the corresponding location to respond and the address is translated into physical page 3.
Therefore on each address generated by the CPU, the following happens with respect to the PMMU logical page registers:
In this example, there will be 8192 pages, which is too many.
A typical PMMU will have 256 pages, so that a page size of 64Kbytes would be more usual with 16Mbytes of RAM.
The access rights distinguish between Supervisor/User, Program/Data and Read/Write accesses. A TRAP is generated if an access is attempted with insufficient privilege.
When all pages have been assigned and a new mapping is required, the O.S. uses an algorithm to determine which page to swap out. A Least Recently Used (LRU) algorithm gives satisfactory results.
Certain fixed pages are required by the O.S. or DMA controller. Flags in the MMU can mark a page as fixed, so that it can't be swapped out.
An active bit in the MMU is set when the O.S. enables a task (in the multi-tasking environment where each process is given a few milliseconds of processor time, in turn). All mappings for the current task are marked as active, and the mappings for all other tasks, as inactive.
Only active mappings will be recognised by the MMU.
This can be done by marking pages as 'fixed' by the PMMU where
address translation can be allowed or
by forcing the PMMU to pass addresses untranslated to the memory.
The MC68010 does retain the required information on the stack when BERR occurs. Thus, when the page fault is fixed by the O.S., the bus cycle can be continued from the point at which it failed. The MC68010, and subsequent processors in this family, was designed to have a virtual memory capability.