RISC architecture
Reduced Instruction Set Computers (RISC) make better use of available
bus bandwidth as instructions are kept short (one word).
This implies a reduced set of simple instructions. The reduction in
the instruction decode and execute logic makes RISC processors smaller,
cheaper and faster than their complex (CISC) counterparts.
RISC processors were developed from the observation that (in a typical
system),
10 instructions accounted for 80% of compiled code and
30 instructions accounted for 99% of compiled code.
These figures arise from statistics derived from the frequency of use
of machine-code instructions which were compiled from a high-level
language (HLL). Since most code on 16/32 bit processors comes from HLLs,
these observations are valid.
CISC processors (e.g. MC68020, 80386 and later processors in those families)
had developed a large set of instructions and addressing modes and resemble
a small "language" in themselves. This makes for easy compiler construction,
but efficieny of use of the microprocessor instructions can be quite low,
especially as compilers are often not sensitive to nuances in the code.
The cost of the extra instructions in a CISC processor, over and above the
most frequently used set, is quite high.
Each extra instruction makes the instruction logic larger and slower.
Making the chip larger has an impact on its cost which rises exponentially
with chip area (because of wafer defects).
As an example, comparable RISC and CISC processors may have
25,000 transistors occupying 5 sq.mm and 200,000 transistors
occupying 16 sq.mm respectively.
Early RISC processors did no more than reduce the instruction set
and simplify the support chips required.
Later RISC processors introduced more pipelining and aimed to achieve
instruction execution in a single cycle.
Other architectures
DSP chips are optimised for digital signal processing functions.
For example, multiplications - with the addition of a single-cycle
multiplier. Multiplications can take over 50 cycles on a conventional
processor.
Graphics chips are optimised for block data transfers and for performing
Boolean operations on data.
Transputers are essentially RISC processors which are optimised for
parallel processing. Special hardware is provided for inter-processor
communications and a scheduler is provided to handle data dependancies.
Custom architectures can be constructed using VLSI or FPGAs which are
now available with over 100,000 gates.
e.g. for 100ns access time, the cycle time is 190ns.
for the same DRAM, the page cycle time is 70ns.
