Bus systems - VME bus, multiprocessor systems

Microprocessor systems often employ more than one processor which can be connected together in a variety of ways. When the system is built onto more than one board, then an inter-processor bus is used.

Arbitration circuits are required a) local to each system and b) for the common (inter-processor) bus. These determine, (a) whether an on-board or an off-board memory access is being requested and (b) whether the inter-processor bus is free. Even if the bus access is allowed, a final arbiter on the target system will decide whether the request resource can be accessed or not.

A number of standard bus systems exist, but the VME bus is used as an example.

VME bus

The VME bus transfers data between two processor systems by the use of a common backplane and control signals. The basic VME bus has a 16-bit address and 24-bit data bus. The extended VME bus increases both these to 32 bits.

The full set of signals is shown below. Only a few signals are required to understand the arbitration process which is used to allow a requesting system to gain control of the bus.

J1/P1 connector

J2/P2 Connector

Pin No ROWa
Signal Mnemonic 		ROWa
Signal Mnemonic 		ROWa
Signal Mnemonic 		Pin No ROWa
Signal Mnemonic 		ROWa
Signal Mnemonic 		ROWa
Signal Mnemonic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 		D00
D01
D02
D03
D04
D05
D06
D07
GND
SYSCLK
GND
DS1*
DS0*
WRITE*
GND
DTACK*
GND
AS*
GND
IACK*
IACKIN*
IACKOUT*
AM4
A07
A06
A05
A04
A03
A02
A01
-12V
+5V 		BBSY*
BCLR*
ACFAIL*
BG0IN*
BG0OUT*
BG1IN*
BG1OUT*
BG2IN*
BG2OUT*
BG3IN*
BG3OUT*
BR0*
BR1*
BR2*
BR3*
AM0
AM1
AM2
AM3
GND
SERCLK
SERDAT*
GND
IRQ7*
IRQ6*
IRQ5*
IRQ4*
IRQ3*
IRQ2*
IRQ1*
+5V standby
+5V 		D08
D09
D10
D11
D12
D13
D14
D15
GND
SYSFAIL
BERR*
SYSRESET
LWORD
AMS
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
+12V
+5V 		1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 		User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O 		+5V
GND
Reserved
A24
A25
A26
A27
A28
A29
A30
A31
GND
+5V
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
GND
+5V 		User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O

To transfer data from one system to another, a) an off-board address is generated, b) the local system arbitrates for the use of the bus, c) when the use of the bus is granted, resources in the the remote system are addressed and d) if the remote system allows reading of the address, the data is returned with a DTACK handshake, else no data is returned and a bus error is flagged.

The arbitration process on the VME bus uses a set of bus request, control and grant lines as shown in the figure.

  1. a board requesting the use of the VME bus asserts /BR0. Assume this is system A3.
  2. The VME arbiter (in left-most slot) asserts /BG0out when the bus is free. This bus-grant is first offered to A2 as a daisy-chained signal. If A2 did not generate the bus request, then it must pass the /BG0 signal on to the next system - /BG0in on A2 is passed to /BG0out.
  3. A3 receives /BG0in and immediately asserts /BBSY (bus busy). /BBSY is held low until the transfer is complete. Either a single word is transferred (arbitrate each cycle) or a block transfer takes place (arbitrate once at the start).
  4. /BCLR can be asserted by the arbiter to force all systems to terminate their use of the bus. This can be used to terminate a long block transfer so that the bus can be used by other systems.

The daisy-chained Bus Grant signals impose an order of priority on the VME slots, with the left-most slot having the highest priority. Missing cards require that a jumper be placed between the BGin and BGout pins for that slot, otherwise the daisy-chain will be broken.

The VME bus has a second level of priority, with 4 Bus Request lines being available. These can be arranged to operate at different priorities at the arbiter, so overriding the slot number priority. In practice, only one Bus Request level is used for most systems.

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